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FPGA基于USB3.0的实时数据采集系统软件设计

时间:2019-11-29 19:30来源:毕业论文
结合ADS4249 芯片的工作时序,编写相应的 Verilog HDL程序进行 AD 端的数据采集及存储的工作,便于后续的数据传输工作; 2、利用 USB3.0 的 CYUSB3014 接口芯片

摘要高速数据的传输系统被广泛应用在许多的电子信息系统中,因而数据在传输过程中的实时性与准确度也成为了人们所关注的热点问题。目前国内外研究了许多的高速传输系统,但大多数都采用了 PCI的数据接口或是 USB2.0 的数据接口。其中 PCI的数据接口拥有 132MB/s 的最大数据传输率,但应用起来却不方便,USB2.0 的数据接口只有480Mbps 的带宽,在高速数据传输实现上有一定难度。USB3.0具有易用性强、数据吞吐率高的特点,传输速率可到达 5Gbps,对解决高速数据的传输问题有一定的研究意义。 本次设计将利用现有的 FPGA硬件平台实现 USB3.0 的高速数据传输,从系统整体的构架出发,分模块分步骤一一进行实现: 1、结合ADS4249 芯片的工作时序,编写相应的 Verilog HDL程序进行 AD 端的数据采集及存储的工作,便于后续的数据传输工作; 2、利用 USB3.0 的 CYUSB3014 接口芯片,根据此芯片在 SLAVE FIFO 模式下的同步读写时序图,并结合工作原理与数据传输协议编写相应的状态机程序,进行数据传输的测试; 3、利用FPGA控制USB3.0 模块与AD数据采集模块,实现 USB3.0块传输协议下的数据流模式与数据包模式。 最后将系统的软件、硬件进行集成测试,利用 Cypress 公司提供的上位机固件程序进行 PC 端数据的收集工作,并利用 MATLAB 软件进行数据的分析,验证整个数据传输系统的正确性。   42231
毕业论文关键词      USB高速数据传输      FPGA       CYUSB3014 芯片                   SLAVE FIFO 的同步读写 
Title  Software  Design   Of    Real   Time   Data   Acquisition   System    Based    On    USB3.0   
Abstract High speed data transmission system is widely used in many electronic information systems, so the data in the transmission process of real-time and accuracy has become a hot issue of concern. At present, many high speed transmission systems have been studied at home and abroad, but most of them have adopted the PCI data interface or  USB2.0 data interface. The maximum data transmission rate of PCI data interface can reach 132MB/s, but it is not convenient to use. USB2.0 data interface is only 480Mbps bandwidth, it is difficult to achieve high speed data transmission. USB3.0 is easy to use and its data throughput rate is very high, the transmission rate can reach 5Gbps, so it is the best means to solve the transmission problem of high-speed data.  This design uses the FPGA platform to achieve high-speed data transmission on USB3.0. According to the overall framework of the system, the following aspects are carried out: 1、According to the work timing of ADS4249 chip, AD data acquisition and storage is achieved by composing the corresponding Verilog HDL program; 2、CYUSB3014 interface chip is used. According to the read write timing of the chip in slave FIFO synchronous mode, and combining with the working principle and data communication protocol. Data transmission is completed by composing corresponding state machine programming; 3、By using FPGA chip to control USB3.0 module and AD data acquisition module, the data flow model and data packet mode of USB3.0 block transmission protocol are realized.  Finally, the software and hardware of the system is integrated to test data transmission. The data are collected by using PC firmware which is provided by Cypress company. MATLAB software is used in order to verify the correctness of the data transmission system.
Keywords   USB high speed data transmission;       FPGA;                        CYUSB3014 chip;           SLAVE FIFO Synchronous reading and writing    FPGA基于USB3.0的实时数据采集系统软件设计:http://www.lwfree.com/tongxin/lunwen_42596.html
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